Honored ContributorHi all!
I would like to define a new kind of bus is SOPC builder, quite similar to the Avalon-ST bus : start of image (1 bit) start of line (1 bit) middle of line (1 bit) end of image (1 bit) error (n bits, configurable) data (16 bits) Is it possible to add a new bus in SOPC Builder or do I have to map this on an Avalon-ST bus ? (I'd prefer to declare a new kind of bus)
Honored Contributorright out of my i would say yes, i remember an avalon specific document that gave some very useful hints about the recomended syntax for custom ip signals that are connected to the avalon switch fabric.
that document recomended to group and name signals so sopc builder & component editor would automatically recognize them (it works!) start naming with avs_ for Avalon Valid Slave, or gls_ for global signal follow by your interface name like myinterface_ if that signal is intended to leave sopc avalon and should be exported to top level add export_ and finaly your custom name, or the avalon signal name you want to connect to like address you will end up with these names for example avs_myinterface_chipselect or avs_myinterface_export_myoutput or gls_clk that document also explained how sopc builder automaticaly connects signals between 2 ips, so sopc builder should be able to do these connections but i am not shure if it would connect a complex bus interfaceHonored ContributorThanks for your answer. Do you remember what this document was?
Honored ContributorI don't think SOPC builder will be able to use a completely user-defined interface that isn't set as export...
Why don't you use some extra error bits to transport the start-of-line and middle-of-line signals? As long as all the components on the stream know about this definition, it should work.Honored ContributorThis is a workaround : mapping my signals to Avalon-ST signals, even if their meaning is different. I could even group all my signals in 'data'.
It works perfectly, but I was wondering if it was possible to avoid this kind of workaround and do things in a clean manner. Also: what if I want to have several signals going from destination to source in addition of 'ready' signal ?Honored Contributorcomponent editor (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf)
Describing the syntax ... but where was the automatic connection described ...Honored ContributorComponent editors does not provide info about custom bus.
It is a tool that helps you generate a _hw.tcl file for your own cores, mapping core i/o names to avalon bus signals. You can either map yourself or respect syntax rules so that the editor does the mapping itself.Honored ContributorI don't think there is any other manner... The interface must conform to the Avalon Stream specification, so I don't se any other way than using data or error bits. And I don't this you can have any other signal than 'ready'
You could also define your own interface standard, declare it as an export, and connect your components yourself outside of Sopc builder. Not really cleaner, but it's a solution...
