default voltage for the cyclone 3 why is 2.5

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when i consult the cyclone 3 datasheet,the VCCIO for c-3 is 3.3V,but when set the pin planner in QUARTUSII or the menu of assignment->device/ device and pin options/voltage tab:default I/O standard is 2.5V ,of course it could change.why for a VCCIO 3.3V chip the default I/O standard in system is 2.5V,a smaller voltage??

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Cyclone 3 provides several settings for VCCIO for each of the IO banks.

The VCCIO that you should use should be the VCCIO as implemented on your FPGA board for that bank and this depends on the I/O standard that you use to communicate with the peripherals connected to the IOs of that bank.

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Cyclone 3 provides several settings for VCCIO for each of the IO banks.

The VCCIO that you should use should be the VCCIO as implemented on your FPGA board for that bank and this depends on the I/O standard that you use to communicate with the peripherals connected to the IOs of that bank.

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sanmao:thanks so much for your help.And for your words ,sound like that if one piece FPGA chip (cyclone 3)work with more than two kinds of level of chip with different bank connected to respectively ,so we should set different VCCIO to the banks that connected ? actually ,i am confused that we set the VCCIO value for the IOs standard through QUARTUSII ,that is nothing with the hardware circuit of the FPGA chip,why there is that kind of settings in the software? To say the least ,if we connect the different bank with different voltage (I mean the VCCIO don't care the VCCINT here)for the IOs ,the FPGA chip would work?just hope for understanding more ,thank you

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why there is that kind of settings in the software

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The VCCIO value is mainly used to calculate IO current strength settings, but it's not changing configuration data directly. Furthermore, Quartus checks the consistency of IO assignments in each bank, e.g. a Bank using LVDS IOs must use exclusively a VCCIO of 2.5V.

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Quartus checks the consistency of IO assignments in each bank, e.g. a Bank using LVDS IOs must use exclusively a VCCIO of 2.5V.

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so ,ONE FPGA chip would still work when we keep each bank the same voltage though different from each bank? as a matter of fact ,didn't meet this situation before.it is so incredible if do this.thanks

If I understood you correctly, the answer is "yes".

Each bank has it's own VCCIO pins that power the I/O elements.

Within each bank, all I/O elements will be powered by the same VCCIO. But different banks can have different VCCIO.

Within each bank, the VCCIO must be compatible with the I/O standards used.

Ie, if you want to use 3.3V LVCMOS I/Os, the bank's VCCIO must be 3.3V.

OTOH, if you want to use LVDS signals, the I/O bank's VCCIO must be 2.5V.

Therefore, you can't mix 3.3V LVCMOs and LVDS signals in the same banks.

You need to use different banks.

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Ie, if you want to use 3.3V LVCMOS I/Os, the bank's VCCIO must be 3.3V.

OTOH, if you want to use LVDS signals, the I/O bank's VCCIO must be 2.5V.

Therefore, you can't mix 3.3V LVCMOs and LVDS signals in the same banks.

You need to use different banks.

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yes ,that was what i mean,and i think i get it now.thanks