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Altera_Forum's avatar
Altera_Forum
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11 years ago

Default port values in SystemVerilog

I am trying unsuccessfully to define a default value for an input port in a module definition, so that if an instantiation of it does not pass a value to that port, the default value is used without ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

You all should be using the ieee 1800-2012 lrm (http://go.mentor.com/get-1800). It's freely available, so there's no excuse for continuing to use other forms.

I can see from the error message that the file has a *.sv extension. I would replace reg with logic to confirm it recognizing SystemVerilog. If it recognizes logic, but not the default assignment, then it has a problem with supporting default assignments.