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Altera_Forum's avatar
Altera_Forum
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17 years ago

Decoding/Executing instructions

So I've learned that I can't use port map statements inside a process block and I'm trying my best to NOT think of quartus/VHDL has a sequential programming language, but I'm kind of stuck on something.

I have two back to back statements: 


decode: regFile PORT MAP(clock,'0',writeReg,RS,RT,RD,writeD,readA,readB);
execute: alufile PORT MAP(readA,readB,opcode(2 DOWNTO 0),shiftAmt,less,equal,cout,writeD);

The decode takes given register# 's and accesses the data in those registers. The second loads the data from those registers into the ALU. The problem is that depending upon the instruction I may not always want the data from two registers to go into the ALU I may want one input to be an immediate. So I have something like this: 


when B=>--decode
			--set up all my registers
			if(opcode = "0001") then --add
			RS<=in1(11 DOWNTO 9);
			RT<=in1(8 DOWNTO 6);
			RD<=in1(5 DOWNTO 3);
			elsif(opcode = "0010") then --ldi
			RT<=in1(8 DOWNTO 6);
			immed<=in1(5 DOWNTO 0);
			readB<=immed;

my idea being that I since I dont have a register, I just want to change the value of the data (readB) that is going into the ALU. I'm just don't think this will work b/c of the timing/order of when things happen. I'm a little confused on that.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I have a problem, that what you present as a "processor model" is permanently changing and it's hard to see what you are trying to achieve as a whole.

    To my opinion, it's not a problem of HDL coding rather than of your designs basic structure.

    I think, it would be helpful to use a structural design approach. As a fundamental fact, you have registers, that take a new value every clock cycle and logic elements, that determine the input to the registers. A basic design decision is in considering, which values have to be stored in a register and how the sequential processing should look like. If you know the structure, you would always be able to code it in HDL.

    You can also use a behavioural approach, but than you must exactly follow the HDL syntax to get the design synthesizable.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    For the most part I do have a structure that I'm trying to follow but merging them together is a little bit tricky. At first I had tried doing all my port mapping in the process block because I didn't know any better and because it made sense sequentially. Now I'm trying to do most of the hardware stuff in the port map blocks and all of the control in the process block. So it's sort of a mix of behavioral and structural. I do know the structure it is just hard to code it in VHDL without modifying preexisting hardware ie. I need to send an immediate to the ALU, not data from a register.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If the input to the "ALU" is unregistered, than it can be selected in a combinational process, not depending on a clock edge. This means immediate assignment of a value.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I'm not sure what you mean by "unregistered" but does that mean that what I am trying to do will work?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    As an example, you have the readB input signal to your ALU instance. You were talking of register signals in this respect, thus I understand the example code is placed in clock synchronous process. Otherwise the signals wouldn't exist as register but be simple wires. 

    immed<=in1(5 DOWNTO 0);
readB<=immed

    If the code above is placed in clock synchronous process, the action would take two clock cycles. Could be shortened to one cycle by making immed a variable instea of a register. But readB would be a register anyway. If readB is intended as immediate input to ALU instance, the assignment must be done in combinational process. I can't see, if this could show intended results, cause I don't know the timing requirements of further processing.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What if I just said readB<=in1(5 DOWNTO 0) ?

    You're right about it being in clock synchronous process. The clock synchronous stuff is supposed to represent the control logic to determine when I'm allowed to do which things in hardware. So I have code like this: 

    
case state is
	
			when A=>--fetch
			writeA<='0';
			writeB<='0';
			writeC<='0';'
			writeReg<='0';
			opcode<=in1(15 DOWNTO 12);
			state <= B;
	
			when B=>--decode
			--set up all my registers
			if(opcode = "0001") then --add
			RS<=in1(11 DOWNTO 9);
			RT<=in1(8 DOWNTO 6);
			RD<=in1(5 DOWNTO 3);
			--etc
			state<=C;
			
			when C=>--execute
			if(opcode = "0001") then --add
			writeReg<='1';
			--PC<=next PC
			state<=A;
			--etc
			when D=>--memory
			if(opcode = "1000") then --lw
			writeReg='0';
			state<=E; 
			--etc
			when E=>--writeback
			if(opcode = "1000") then
				writeReg<='1';
			--PC<=next PC
			state<=A;	
			end case;

    Basically my control has to go through the different stages. In case B I've set up all the registers but since all of my portmaps happen at the same time everytime, I'm not sure that saying readB<=etc is what I want to do to get an immediate value into my ALU