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Altera_Forum's avatar
Altera_Forum
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12 years ago

declaring port as array type

How to solve a problem with declaring port as array type?

I want to make entity multiplexer like this: 

entity multiplexer is
    generic(
        sel_bits: integer := 2;
        data_width: integer := 1
    );
    port(        
        input: in array (2**sel_bits-1 downto 0) of bit_vector(data_width-1 downto 0);    -- this won't do. I could use package, but is there this kind of solution?
        output: out bit_vector(data_width-1 downto 0);        
        sel: in bit_vector (sel_bits-1 downto 0)
    );
end entity multiplexer;

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    you cannot declare an array like that. First you need to declare the type and then create a signal of that type. In this case you will need to declare the array type in a package.

    type my_array_t is array(2**sel_bits-1 downto 0) of bit_vector(data_width-1 downto 0);

    --in the port

    input : my_array_y;

    The upshot of this is that you will need to decalre the generics as constants in the package also.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Or for more flexibility you could define your own array type using an unconstrained array (VHDL-2008). Define it in a separate file like this: 

    type StdLogicVectorArray is array(integer range <>) of std_logic_vector;

    Include it in the library section 

    library work;
use work.MyTypeFile.all;

    Now you are able to use it for your port like this: 

    port(
   input : in	StdLogicVectorArray(0 to (2**sel_bits-1))((data_width-1 downto 0) downto 0);
   (...)
);

    Hope that helps.

    Regards, Sören
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I was hoping it would help, but 

    type StdLogicVectorArray is array(integer range <>) of std_logic_vector;

    isn't correct. It says that std_logic_vector is unconstrained, or something like that... When I try to constrain it with 

    type StdLogicVectorArray is array(integer range <>) of std_logic_vector(0 to 100)

    and use it in code like this 

    port(
       input : in    StdLogicVectorArray(0 to (2**sel_bits-1))((data_width-1 downto 0) downto 0);
       (...)
         );

    it complains that element type in StdLogicVectorArray is constrained, so I can't do that.

    Now what?