Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

declaring port as array type

How to solve a problem with declaring port as array type? I want to make entity multiplexer like this: entity multiplexer is generic( sel_bits: integer := 2; data_width:...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Or for more flexibility you could define your own array type using an unconstrained array (VHDL-2008). Define it in a separate file like this: 

type StdLogicVectorArray is array(integer range <>) of std_logic_vector;

Include it in the library section 

library work;
use work.MyTypeFile.all;

Now you are able to use it for your port like this: 

port(
   input : in	StdLogicVectorArray(0 to (2**sel_bits-1))((data_width-1 downto 0) downto 0);
   (...)
);

Hope that helps.

Regards, Sören