declaring port as array type

I was hoping it would help, but

type StdLogicVectorArray is array(integer range <>) of std_logic_vector;

isn't correct. It says that std_logic_vector is unconstrained, or something like that... When I try to constrain it with

type StdLogicVectorArray is array(integer range <>) of std_logic_vector(0 to 100)

and use it in code like this

port(
       input : in    StdLogicVectorArray(0 to (2**sel_bits-1))((data_width-1 downto 0) downto 0);
       (...)
         );

it complains that element type in StdLogicVectorArray is constrained, so I can't do that.

Now what?