Decision scheme

Hi ,

I design decision scheme in order to determine whether the signal i '0' or '1' from group of 4 bits and then the output signal of the scheme change respectively .

for some reason the output signal Des_out is persistently '0' .

The VHDL code is :

--process - decision scheme '0' or '1'

process (ResetP)

variable score : integer range 1 to 4;

begin

score := 1 ;

if ( resetP = '1' ) then

Des_out <='0';

elsif ( clk_100M'event and clk_100M='1' ) then

for ind in 0 to 3 loop

if hlp(ind)='1' then

score := score + 1;

end if ;

end loop ;

if (score > 2) then

Des_out <= '1';

else

Des_out <= '0';

end if ;

end if ;

end process;

what is wrong in the design ?why does Des_out is consistently '0' ?

does the design have to be depend in the clock event or it will change for every change in the group of 4 bits ?

how can i watch at variable score and ind during the simulation ?

Visio file attached - look at Desicion scheme (the rest is at other process) .

wave photo attached - Des_out = '0'