Honored Contributor
Honored ContributorI have changed these designs in the past, and here's the procedure I followed;
First I start with a standard design, and if required modify the pin assignments to match my specific hardware, synthesize and confirm there are no issues, eg., constrain any unconstrained paths (like JTAG). I then test this in hardware to confirm I have a known-good reference design. I'll then often change the data rate of the links for tests. I then modify this known-good design. Eg., add new transceiver blocks, along with their data pattern generator and checker cores into Qsys, generate the new Qsys system, synthesize (to check it works), then using the Pin Planner I make the pin assignments, and re-run synthesis. You did not comment about making pin assignments - did you make sure you updated those correctly? The Transceiver Toolkit GUI is broken in 14.0. It does not work correctly. I have to delete the channels that it automatically creates, and then use the Setup button to create them. I then save that as a Tcl script and reload it next time I run the test. I've been testing with Stratix IV and Arria V GZ devices. The Arria V GZ devices have the same transceiver IP as the Stratix V. Your description above sounds correct. I don't see why you do not see the additional channels. I assume you downloaded the updated design? Cheers, Dave
