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Altera_Forum's avatar
Altera_Forum
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11 years ago

Debounce Verilog ( I have some questions)

hello everyone. i'm new to verilog programming. i have some questions on debouncer. I already get the concept of debouncing. but how do i compute for the length of the register that i would be using....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You can keep on using the 24mhz clock and 8 sample. You can simply define a counter and inside the always @(posedge clk) process you place the sampling in a conditional statement. For example:

counter <= counter + 1;

if (counter == 1000)

begin

<sample here the input>

counter <= 0;

end