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Altera_Forum's avatar
Altera_Forum
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10 years ago

De2 Verilog HDL LCD coding problem

Good day. we are currently doing a project using altera de2 that requires us to use the lcd. we have 3 .v files and VErilog3 is our top module. module Verilog3( //////// CLOCK //////...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The DLY_RST is not connected to anything at the top level. Maybe it should be driven by the Cont register?

Have you tried simulation? I think it is a simple state machine that you can validate its functions in modelsim. Note that the always for case LUT_INDEX is missing sensitivity list at the always.

Either become always @ (*) or always @ (LUT_INDEX)