DE2-115 media computer verilog top level entity to VHDL

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That top level is little more than a port map. Plus Quartus supports mixed language. So why bother re-writing it to VHDL?

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As I said, I want to edit the given verilog. I could add a VHDL file that has a DE2_115_Media_Computer component but i'd rather not retype all those inputs and outputs to VHDL since that would take a long time. I was just wondering if someone else has already converted this or if there is an automated way to convert verilog to VHDL. If someone has a DE2_115_Media_Computer component with a port map and an entity that'd be great too.