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Altera_Forum's avatar
Altera_Forum
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12 years ago

DE2-115 DDR2 Controller

Hi everyone!

I'm currently working on an implementation that requires me to store packets into the SDRAM then fetch it when it is optimal to transmit. I am having trouble on making it work though.

The way I understand it, I have two options.

  1. Use NIOS through QSYS then access the memory using C programming.

  2. Use AVALON INTERFACE and MegaWizard to generate the necessary IP.

What I have done so far:

for the nios:

Introduction to the Altera Qsys System Integration Tool

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/introduction_to_the_altera_qsys_tool.pdf -- use this until the part of compilation. stop in the step where altera monitor is being discussed. it is already outdated and is replaced by a built in eclipse.

Using the SDRAM on Altera’s DE2-115 Board with VHDL Designs

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/vhdl/de2-115/using_the_sdram.pdf -- this completes the whole nios system with sdram. problem at this point is how to access the sdram now that it has a controller. tutorial did not give any insights about doing this

i want to extract the data from the memory to a logic outside the nios system. in essence, i am just using the nios to access the memory because this is the easier tutorial that i have found online. however, it lacks the succeeding steps.

for the avalon:

AVALON MEMORY MAP INTERFACE

Chapter 3. Avalon Memory-Mapped Interfaces

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

Embedded Peripherals IP USER GUIDE

Chapter 2. SDRAM Controller Core

http://www.altera.com/literature/ug/ug_embedded_ip.pdf

External Memory Interface Handbook - Volume 2: Design Guidelines

Chapter 9. Implementing and Parameterizing Memory IP

http://www.altera.com/literature/hb/external-memory/emi_plan.pdf

From this, I have deduced that the SDRAM controls will be handled by the IP built by Altera, and the only thing that I should have problem is utilizing the Avalon-MM Slave Port. This might be a good idea for developers who are already familiar with altera because the Avalon interface is used in many IP but since this is my first time to use such interface, I am lost on how to proceed.

i know that this is a more straight forward approach but i can't find the right timing diagram to create an fsm that will utilize the signals. moreover, i need more information on each control and data signals. on top of that, during the creation of the ip with megawizard, i don't have any idea on what to put into the parameters of the sdram because the de2-115 did not specify what chip it is.

Here are the information that I know about the SDRAM in DE2-115.

  • DDR2 - 128MB

  • 16 data lines shared for both SDRAM making it access 32 bit of data per address locations.

  • It has 13 address lines and 2 address lines for the banks.

  • Address Banks = (2^13) (2^10) (2^2) = 8192 1024 * 4 = 33554432 address locations = 32M

  • 32M words x 32 bits/word = 1028 Mbits = 128MB

I'm glad to have any help from either approach. I've been stuck here for almost two weeks. I tried my best to gather all the information that I can but it is not enough. I hope someone can enlighten me about DDR2 addressing.

Many thanks!

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    It's easy: every byte on Avalon-MM interface is addressed. So you just need to think about write/read operations on Avalon bus. The rest is done by DDR2 controller. On chapter 3 you have all the needed info to design your Avalon Master: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

    The datasheets (for SDRAM too) for your board are here: http://www.altera.com/education/univ/materials/boards/de2-115/unv-de2-115-board.html -> a *.zip file for download in the bottom.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you sir linas for pointing out the .zip file. I missed that one. I just realized that the SDRAM is not a DDR. I think the ones in the controller in the MegaWizard will not work for the SDRAM of the DE2-115. Do you have any idea on how to complete the logic with the AVALON interface using QSYS?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I mean there is no mention of DDR in the Datasheet. I assumed that the SDRAM is a Single Data Rate DRAM. Please correct me if I am wrong.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I'm referring to this difference:

    Single data rate (SDR) SDRAM is the older type of memory, commonly used in computers prior to 2002.

    Double data rate (DDR) SDRAM hit the mainstream computer market around 2002 and is a straightforward evolution from SDR SDRAM. The most significant difference between DDR and SDR is that DDR reads data on both the rising and falling edges of the clock signal, enabling a DDR memory module to transfer data twice as fast as an SDR memory module.

    SOURCE: http://www.crucial.com/kb/answer.aspx?qid=3773
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    SDRAM stands for synchronous dynamic random access memory and says nothing about data rate. It may be single data rate or double data rate. SRAM stands for static random access memory, what says us, that it does not need refresh.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Yes, I know. However, since the datasheet did not say that the SDRAM is a DDR then I assumed that it is an SDR.

    ---

    Single data rate (SDR) SDRAM is the older type of memory, commonly used in computers prior to 2002.

    Double data rate (DDR) SDRAM hit the mainstream computer market around 2002 and is a straightforward evolution from SDR SDRAM. The most significant difference between DDR and SDR is that DDR reads data on both the rising and falling edges of the clock signal, enabling a DDR memory module to transfer data twice as fast as an SDR memory module.

    SOURCE: crucial<dot>com -- I can't post links without the moderator checking the content for now.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    There is written in datasheet, that inputs are acquired only on rising edge of the CLK signal.

    --- Quote End ---

    That means it is an SDR SDRAM right sir?

    ---

    I do want to use the Avalon interface and that is my main problem now. With the device being a SDR SDRAM, there is no controller in MegaWizard which is pretty straight forward in terms of creating IPs unlike QSYS that you have to make the connections. I don't want to use the NIOS because I want a more straight forward approach but I can't find the proper AVALON component to match the "Avalon Memory Mapped Master" of NIOS.

    As stated in my initial post, after completing the system with NIOS, I have no clue on how to proceed on using the SDRAM memory through NIOS. I am still looking into this if this proves to be an easier route than understanding the AVALON MM Interface but I can't find a good tutorial on doing either.

    Thank you for you insights :)
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I clearly see in my QSYS a component called "SDRAM Controller". You have 2 options: export Avalon MM interface from QSYS to Quartus or add your custom peripheral to QSYS.