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It may very well be that the design is too big. I know for a stratix V, the matrix multiplication is ~70% utilization without modifying the kernel. For a cyclone V soc, which i think is the FPGA on that board, is much much smaller. One thing thing you can do is look at the area.rpt in your compile directory to see the utilization of the design (or compile with --report) to see if the resource utlization is over 100%.
Otherwise, try to decrease the size of the matrix multiplication by decreasing the block size in the header file. This should result in a much smaller design. Instead of 64, try 16 or smaller.
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Thanks for the response! I'll try compiling with --report now, it just bothered me that I can't even run sample code. However, knowing both that Altera has many different OCL boards and that they are probably trying to push the limits of them and others, I shouldn't be too upset that it's such a big design it can't fit on my board.
I was just thinking that I was doing something wrong rather than it being a limitation of the hardware.
Now to figure out how to compile SDL for arm...
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