Honored ContributorHi,
I begin to use Quartus 15.0 and Qsys. I want create a ADC project. I use Qsys tools. I put CPU : Nios II (Classic) Processor. When I quit Qsys tools, i have this error (I didn't generate): http://www.alteraforum.com/forum/attachment.php?attachmentid=11436&stc=1 I try to finish my Qsys project and i have the same error. Thanks for your help Jennifer
Honored ContributorHi,
I haven't error NOW. it must not use Classic Processor but "Nios II Processor". I generate with synthesis "Verilog" BUT same error sip and qiq files I will test with 13.0 version and after open my project with 15.0 version JenniferHonored ContributorHonored ContributorNote that NIOS code execution must start in a place that has code at power on. This is either flash which has been programmed in advance or on chip memory which has been initailized with a memory init file. You cannot set the reset vector to DDR as it won't have been initialized.
Honored ContributorHi,
1) "You cannot set the reset vector to DDR as it won't have been initialized" How can I initialise this ? 2) I tested with a Linux PC and i have the same errors. If someone can help me, i can send a zip file of my project (windows, i prefer) or make my begin project ?? Thanks JenniferHonored Contributor1) Normally you don't initialize DDR. You make a small piece of on-chip memory and put your reset and exception vectors there. You can put the code in on-chip memory and the data in DDR if you like. If your code is too big to fit on-chip memory, you will need a small boot loader to do this. There are tutorials and some videos on how this works on the Altera website.
2) Linux vs PC won't matter. Your problem is that you are trying to run out of DDR which has nothing (or garbage) in it. You need to run out of on-chip memory or flash which has already been programmed.Honored Contributorare you still running into the same problem now?.
