Forum Discussion
DBart1
New Contributor
7 years agoDDR3 MPFE timing constraints
I am using the Cyclone V DDR3 IP core with hard memory controller and Uniphy. I am using multiple ports, using the MPFE feature, and the ports are clocked by unrelated clocks. Timequest is reporting ...
NurAida_A_Intel
Frequent Contributor
7 years agoHi DBart1,
The KDB is published after the IP released. In other word, the bug/issue were encountered after the IP released. The IP UG sometime is not updated anymore especially for old device. So, KDB page is use as the platform to update the user about the known issue.
I sincerely apologize for the inconvenience caused.
Regards,
NAli1