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DBart1's avatar
DBart1
Icon for New Contributor rankNew Contributor
7 years ago

DDR3 MPFE timing constraints

I am using the Cyclone V DDR3 IP core with hard memory controller and Uniphy. I am using multiple ports, using the MPFE feature, and the ports are clocked by unrelated clocks. Timequest is reporting ...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Dear DBart1,

Thank you for joining this Intel Community. I am truly apologize for the delay in response due to long holiday in my region.

The issue you are facing is a known issue but it is not fix in the IP. As a workaround, we have published a KDB on how to cut the failing path in this link --> https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd08142014_213.html

Hope this helps.

Thanks

Regards,

NAli1

DBart1's avatar
DBart1
Icon for New Contributor rankNew Contributor
7 years ago

Is the KDB mentioned somewhere in the User guide or other place that I missed? I am a little confused when using the IP what information is needed to be reviewed. There are 364 KDB articles that show up when search for DDR3. Why wouldn't this be mentioned in the IP User guide if it is a known issue?