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Altera_Forum's avatar
Altera_Forum
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15 years ago

DDR3 Controller with UniPHY

I am designing FPGA system for Altera's Stratix IV GX development kit (http://www.altera.com/products/devkits/altera/kit-siv-gx.html) using Altera Tool Suite v10.0 SP1. I have attached screenshot of SOPC builder system content (sys_cnt.jpg). I am seeing a strange warning on bottom pane "Warning: timer_1ms: Period validation cannot be done because input clock is unknown."

I think this warning appears because timer core is not able to recognize clock generated from DDR3 controller core. And so when I try to generate this system I receive error, error details is attached in second image (sys_gen.jpg).

Does anyone know about this issue? If yes, is there any way to fix it?

Regards,

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Ketan,

    If you haven't resolved this issue, one thing that is recommended by Altera and seems to work for me always is to push your ddr3 core related sdc files to be the first files. Generally, these files are included in the .qip file generated along with your files. Atleast this is what I get with megawizard flow. So what I was told to do was to push it to be the first file in the file order.

    Like many things in Quartus, it's funny how it works but there isn't a way to explain it.... I am paraphrasing Altera's FAE.

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Actually, the design is done long time ago. Anyways, thanks for your inputs.