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Honored ContributorDDR3 - Connecting 2 masters to one slave in QSYS
Hello, I have a DDR3 controller thats implemented in QSYS. The Avalon MM bus of the DDR3 has 2 masters connected to it: the ARM HPS and my custom logic. My question: Suppose the HP...
Altera_ForumHonored Contributor
Honored ContributorMaster B will not see the answer.
I believe under some circumstances the 'readdata' might have the data destined for the other master, so you could maybe snoop it, but no, your custom logic 'readdatavalid' would not be asserted.
