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Maybe You can share the project (if it's not a commercial secret of course), so someone on the forum could also compile and test the results?
I am also planning a Cyclone III EP3C40 + DDR2 system, but if it eats so much logic, it doesn't make sense then...
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It is a run of the mill Qsys thing:
ddr2 - a single MT47H32M16HR-25E
internal static memory 4kB
TSE
SGDMA Rx, Tx
Nios II/s
SpiMaster (connecting a small external supervisor micro-controller which also accesses all MM slave ports)
Pio 4 pc. to test the FPGA IO
all this in an EP4CE30F23C8N, consuming 22033 LCs of the 28k+ available ...
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