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Altera_Forum
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15 years ago

DDR Diff Clock Assignment Woes

The QII HPC Megafunction Wizard generates a HPC controller block with the differential mem_clk[1..0] and mem_clk_n[1..0] outputs for my SO-DIMM design. This causes not four but EIGHT signals because ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

So in short, the correct solution is to set all differential DDR2 signals as SSTL 1.8 single-ended, route out all signals to pins and explicitly assign the pin locations in the pin planner?

Just need to verify so i don't shoot myself in the foot!