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The confusion is in that memclk[1..0] have been assigned a Differential SSTL IO standard. In that case the memclk[1..0](n) pins are implied and handled by Quartus. But as the HPC has both a memclk[1..0] and memclk_n[1..0] you have to change the Differential assignment into the single-ended. You can then assign locations for memclk_n[1..0], which BTW happen to be the ones previously used by the memclk[1..0](n) signals.
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But if this is done, would not the timing between memclk and memclkn differ since the memclkn signals would be sourced from the internal FPGA logic and not from the IOE? I would assume it would then be up to me to (somehow) add SDC constraints to keep the timing between the two clocks synchronized?
I think this is the correct way to handle this:
I ended up keeping the megawizard-assigned differential clocks and simply not assigning the memclkn pin locations. In fact, i removed them from the pin planner and only assigned the positive parts of the clock pairs in the pin planner - the pin planner then automatically assigned the complement signal. My design niow compiles and timing analysis passed.
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