DCFIFO sample duplication problem

I was referring to my testbench. I included a simulation of the FTDI in verilog (it's basically a simulation of the FTDI and the USB bus, since it generates data for the FTDI to send to the FPGA at set times / frames of data) in one of my testbench files.

In case a transfer is corrupted, a reset sequence can be sent which will resync the FPGA (basically just 0xFF, and enough bytes to be longer than any other command, including attached data). However, unpugging the device while a measurement takes place souldn't be done anyways.

Reading data in general does work. The bug(s) reside(s) only in the FPGA to FTDI interface (upstream), as it seems.

Your's sincerely,

Felix Lembcke