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The reason is the device (FTDI USB chip) I'm interfacing with. It signals me wether it can accept any more data on the rising edge - so it takes at least one cycle to see wether my write access was successful or not. Then, if the FIFO would also run on the positive edge, it would take another cycle untill the FIFO get's notified that it shouldn't provide more data.
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Which FTDI device and which mode? The FT245 and FT2232 devices have an asynchronous FIFO mode, while the FT2232H device has a synchronous FIFO mode. If you're interfacing to the FTDI device in asynchronous FIFO mode, then you need to run the FTDI signals through synchronizers before using them, so the FPGA clock is basically independent of the FTDI device. I haven't used synchronous mode, though I do have an FT2232H module I've been planning on testing one of these days ...
Cheers,
Dave
Honored Contributor
