Honored Contributor
Honored ContributorThe reason is the device (FTDI USB chip) I'm interfacing with. It signals me wether it can accept any more data on the rising edge - so it takes at least one cycle to see wether my write access was successful or not. Then, if the FIFO would also run on the positive edge, it would take another cycle untill the FIFO get's notified that it shouldn't provide more data.
In that case, I would need to keep track / store up to 3 "old" data samples. I guess this could be done with pipelining, but since I'm working with a Stratix Device and the clock is "only" 60MHz, there are no timing issues with the alternating clock edge logic. Since the access to the FTDI is bidirectional, this is quite complicated the way it is already. Thanks for Your advice nonetheless. Your's sincerely, Felix Lembcke
