DCFIFO readings incorrect using different reading clock

Hi,

I am attempting to use DCFIFO megafunction in my design, but two problems met:

1. the rdempty signal always keep high, and rdusew signals don't function, too. so I can't read data from FIFO. after checking the wrempty and wrusew signals, they function correctly, so I use wrusew to detect and correctly got the desired.

2.even when use wrempty or wrusew signal, the reading data is not exactly the same as what I wrote if rdclock is different from wrclock.

following is my verilog codes:

innerFIFO innerFIFO_inst (

.aclr ( innerFIFO_clear ),

.data ( innerFIFO_datain ),

.rdclk ( innerFIFO_rdclk ),

.rdreq ( innerFIFO_rdreq ),

.wrclk ( innerFIFO_wrclk ),

.wrreq ( innerFIFO_wrreq ),

.q ( innerFIFO_dataout ),

.rdempty ( innerFIFO_rdempty ),

.rdusedw ( innerFIFO_rdusedw ),

.wrempty ( innerFIFO_wrempty ),

.wrusedw ( innerFIFO_wrusedw ),

.wrfull ( innerFIFO_wrfull )

 );

//

wire innerFIFO_wrfull;

wire innerFIFO_wrempty;

wire innerFIFO_rdempty;

reg innerFIFO_clear;

reg innerFIFO_rdclk;

reg innerFIFO_wrclk;

reg innerFIFO_rdreq;

reg innerFIFO_wrreq;

wire[14:0] innerFIFO_wrusedw;

wire[14:0] innerFIFO_rdusedw;

reg[15:0] innerFIFO_datain;

wire[15:0] innerFIFO_dataout;

always @(posedge Wr_clock) //line 26 for FIFO reading

// always @(posedge rd_clock) replace line 26 with this line, wrong readings when rd_clock is a little bit faster or slower

// readings are correct only when both reading and writing clocks are exactly the same

begin

case(USBwriting_state)

USBwriting_ready:

begin

if (USBnofull )

begin

innerFIFO_clear<=0;

innerFIFO_wrreq<=1'b1;

innerFIFO_rdreq<=1'b1;

if(innerFIFO_wrusedw>4)//line 46

// if(!innerFIFO_wrempty) replace line 46 with this line, works

// if(!innerFIFO_rdempty) replace line 46 with this line, not work,

// rdempty keeps high no change

// if(innerFIFO_rdusedw>4) replace line 46 with this line, not work

begin

innerFIFO_rdclk <= 1'b1;

USBfifo[15:0]<= innerFIFO_dataout[15:0];

USBwriting_state<=USBwriting_write;

end

end

else

begin

USBwriting_state<=USBwriting_full;

end

end // end of writing_ready

USBwriting_write:

begin

innerFIFO_rdclk <= 1'b0;

USBwriting_state<=USBwriting_ready;

if (USBnoempty)

begin

USBfifo<=16'bz;

end

end

USBwriting_full:

begin

if (USBnoempty)

begin

USBfifo<=16'bz;

end

USBwriting_state<=USBwriting_ready;

end

default:

begin

USBwriting_state<=USBwriting_ready;

end

endcase

end

always @(posedge Wr_clock) //FIFO writing

begin

case(FIFOwriting_state)

FIFOwriting_ready:

begin

if (!innerFIFO_wrfull)

begin

innerFIFO_wrclk <= 1'b0;

innerFIFO_datain[15:0]<= ADCIdata;

FIFOwriting_state<=FIFOwriting_write;

end

else

begin

FIFOwriting_state<=FIFOwriting_full;

end

end

FIFOwriting_write:

begin

innerFIFO_wrclk <=1'b1;

FIFOwriting_state<=FIFOwriting_ready;

end

FIFOwriting_full:

begin

if (!innerFIFO_wrfull)

begin

FIFOwriting_state<=FIFOwriting_ready;

end

end

default:

begin

FIFOwriting_state<=FIFOwriting_ready;

end

endcase

end

//

Thanks