DCFIFO megafunction simulation problem

You are very mistaken. Your read clock and write clock should be using the same clock as the data (even if the data is comming in serially) and then the wr-req is high when the data is ready. It is the write request that enables the data into the fifo, not the clock. There is other logic inside the fifo that requires that the clock is always running, not just when you need to write data in (like the address counters, and the logic to cross the counters over the clock domain boundaries).

As for lookahead mode, it basically removes an output register from the fifo. With lookahead mode, you use the read request as an acknowledge rather than a request (ie. the q output is valid until you assert rdreq) and with lookahead off, the data only appears when rdreq is assertert, and valid until rdreq is asserted again.

I suggest you read up on the fundamentals of digital logic.