DCFIFO megafunction simulation problem

First of all, I somehow fixed the problem I was having simply by switching to show-ahead mode. Why did this work? That tells me that the problem was with the read cycle rather than the write cycle.

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secondly - why is the data changing at a much faster rate than the write clock?

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Tricky, I am reading in data one bit at a time, causing the write data to change at a faster rate. than the write clock. Only once all 8 bits have been read in does the "clock" sample the data. I need to check some bytes of the the data that is coming in, which is why I form words and then send the data to the FIFO, as opposed to having a FIFO that takes in one bit at a time.

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first of all, why are your clocks not clocks (50-50 mark space ratio?)

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Again, I am reading in data one bit at a time, and this data rate may change, or the stream of bits may be delayed for some reason, so the write clock signal is asserted only when a new byte of data is available to be written to the FIFO. The same goes for the read "clock". As far as I am aware, it is only the rising edge that matters when writing / reading. Am I wrong? Should I extend the HIGH period of my "clocks"?

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thirdly - in the first picture I cannot see any of the input data.

in the second I cannot see any of the rd data in the write data stream.

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I'm aware of this. Which is why I put in both pictures. Perhaps I should have explained that the second is a zoomed in version of the first, so you can see the final few write cycles of the clock more clearly. The both show the final few read / write cycles of the FIFO. If you look carefully you'll notice that the last few words written (in the second image) match the last few words read (in the first), with the exception that the last word is missing from the read cycle. This is my problem.

Yeah, I know I'm not using the FIFO completely correctly, and that's the reason for this post. But I am getting 255 of my 256 test words behaving correctly through the FIFO.

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Probably wrreq signal is misplaced with wrclk...

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As shown in the images, the wrreq signal is asserted the entire time. Can this still be the problem? I have turned on overflow and underflow protection, if that helps.