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Altera_Forum's avatar
Altera_Forum
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17 years ago

Data skew constrain

In my design I need to sample the incoming serial data in 8 different registers simultaneously. The registers are clocked by different clocks (8 different phases of one clock). The design should sele...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Come into the input, then feed your 8 F/F and floorplan the 8 F/F to be right next to the I/O cell on the die.

This should help control the route delays.

The real challenge is that you will be using 8 different clocks (related by phase), each FF will need to be in a different LAB.

To help control the route delays, you can then set a very "almost" undo-able SDC constraint on the incoming part to force the tool to work real hard to meet all the parallel timings. (turn on timing driven options).

Good luck with this, and keep us informed.