Data Clock Race conditions

Hi Niki,

Thanks for the reply.

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Hi,

If your whole system runs from one physical clock source, then this should not not happen and the problem has to lie elsewhere.

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The transfer is being done source synchronous (i.e. the clock travels with the data so it is the same clock, but somewhat delayed of course. I am able to run the brd 2 brd comm system correctly at 48MHz, but not at 50MHz. Would have loved it if it had worked at 50 though.

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Hi,

If your intention is to have the two systems run from completely asynchronous clocks, then the safest way to cross the clock domains is with a dual clock FIFO. The simple two FF synchroniser is good for passing a single control signal, but when passing multiple signals (like data bytes), the FIFO is the safest.

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I see your point there. A bi-sync FIFO is definitely the most suitable way. But the simple two FF synch is also good enough to do the job. The single control signal that is passed using the 2 FF synch, is used as a flag by the rx side to know exactly when there is stable data on the data lines. Delay of one cycle placed in by the 2 FFs ensures that we never enter metastability.