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Altera_Forum
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16 years ago

Data Clock Race conditions

Hello everyone,

I am trying to connect two Altera Stratix II boards together through a custom 2-bit serial connection. Right now I send the clock (along with the data) from board 1 to board 2 so that the data can be sampled at the same clock remotely. Then I perform a clock domain translation on board 2 using a two-flop synchronizer.

The problem is that the data bits sent out from board 1 (as seen on the Logic Analyzer) are different from the data bits received on board 2 (as seen on LA). I am using the same clock to run both LAs so I assume the data bits should appear to be the same.

Since they are not, so I thought there must a race condition occurring between the clock and the data so I started sampling on the neg edge of the clock on board2. It has improved, but still sometimes the data bits are skipped or received twice. Entire system operates on a standard 50 MHz clock... I have tried many different things but its still not stable. Any suggestions/advice would be highly appreciated.

Btw, in the info after compilation the following msg is shown where sys_clk is the board 1 clock and sndr_clk_UR_LR_A is the signal that carries the clock to the remote board:

"Info: Longest tpd from source pin "sys_clk" to destination pin "sndr_clk_UR_LR_A" is 11.467 ns

Info: 1: + IC(0.000 ns) + CELL(1.063 ns) = 1.063 ns; Loc. = PIN_AF15; Fanout = 2; CLK Node = 'sys_clk'

Info: 2: + IC(8.021 ns) + CELL(2.383 ns) = 11.467 ns; Loc. = PIN_C21; Fanout = 0; PIN Node = 'sndr_clk_UR_LR_A'

Info: Total cell delay = 3.446 ns ( 30.05 % )

Info: Total interconnect delay = 8.021 ns ( 69.95 % )"

Thanks in advance !!!

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Minor correction:

    Data bits are sometimes received twice when sent from Board 1 to Board 2, and are skipped some times on the reverse path.

    Please ask if I missed any related detail. Thanks !
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I will first make sure my serialiser/deserialiser functionality is correct.

    If so then it will point to a timing problem. Make sure you are using fast i/o output registers and possibly a dedicated clk output pin. A practical test is to send your clk from a pll and rotate the phase to optimise the timing window.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I am not sure why you use two stage synchroniser since your case is that of source synchronous transfer.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the reply !

    I have verified the functionality many times and if used on the same board using the same clock, there are no issues !

    "Make sure you are using fast i/o output registers and possibly a dedicated clk output pin. A practical test is to send your clk from a pll and rotate the phase to optimise the timing window."

    That I am not doing ! How do I use the fast I/O registers ??
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The network right now is mesochronous but the intention is for the design to be portable to completely asynchronous networks with minor changes. Thus once the serial data is converted to a full packet, it is passed through a two-flop synchronizer to translate the clock domain without entering in to any of the metastability issues. That part seems to be working ok, the problem is that the bits do not appear to be the same as the ones sent !!

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Quartus doesn't use io registers by default.

    to use i/o registers go to assignment editor, select your nodes then enable fast output registers on your data and clk and and enable fast output_enable register if you are using this. For the other board enable the fast input register for data.

    For PLL, instantiate one, and either manually change phase per build or you can go for the dynamic phase feature...

    Make sure you are testing your data before any clk domain crossings in the Rx board.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    One more thing,

    add Tco constraint to your outputs(data and clk) otherwise the fitter will swing around from build to build.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I am using Quartus 7.1 - After I select the nodes in the assignment editor I cant seem to find the option that is used to set the fast I/O registers -- how does one do that?

    Also can you please be a bit more specific in terms on where to find the option for setting the Tco constraint ! Thanks !
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Xinjia,

    How long is that cable between the boards?

    If it is not properly terminated, you may see bits and clocks bouncing back and forth between rx an tx. The longer the cable, the more corruption that causes.

    If you have a fast oscilloscope, see the analog waveforms near the rx.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Once you select a node you get many options in the form of spreadsheet style. It will be named "fast input register" and the next cell choose "enable"

    or it could be "fast output register" and so on...

    Tco is also one of the options.

    remember Tco and PLL rotation can be conflicting to the fitter. You will need to see what actual figures are finally accomplished by the fitter.

    your signals must be registered for this option.

    Alternative to assignment editor, use commands(there are several example around, can't remeber from top of my head now).