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I do have conversion libraries
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Which ones? For math, you should use numeric_std and math_real, not the older std_logic_arith libraries.
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Sorry for not posting the whole code, this snippet is part of a huge module that I'm upgrading.
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That's ok, but when paring down code, synthesize it before posting it, as then the compiler performs the first level of syntax checks.
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I have to remind myself of the strict type checking in VHDL.
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I think its a good thing. There is much less ambiguity when reading code other people have written.
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Also elsif is interesting, didn't know there was a difference. That could also be a problem that I'm facing.
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There's also another factor. The tool. The style of code that I wrote infers a register ... perhaps the style you wrote does not. The way to answer that question is to look at the synthesized output. In Quartus there is an RTL netlist viewer which draws a schematic of your circuit. Use it to look at how Quartus interprets your code vs my code ... perhaps its identical. (Tools->Netlist Viewers->RTL Viewer).
Use both Modelsim and Quartus while learning about FPGAs and HDLs. Feedback is good :)
Cheers,
Dave
Honored Contributor
