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Altera_Forum's avatar
Altera_Forum
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12 years ago

D Flip Flop

Hi All, I created a simple VHDL D flip flop but saw strange results on the logic analyzer. The code is as follows: df:process(reset,clk) begin if(reset='1') then ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks for the quick reply Dave. I do have conversion libraries, and in the original code I initialize the output to a signal, not to a constant. I just put that constant in as an example of what I was doing. Sorry for not posting the whole code, this snippet is part of a huge module that I'm upgrading.

I think the problem is that in my code I only check if (A AND B ), not ((A='1') AND (B='1')). I have a lot experience in verilog which allows you to do that with no problem. I have to remind myself of the strict type checking in VHDL. Also elsif is interesting, didn't know there was a difference. That could also be a problem that I'm facing. Finally, I could probably lose the Q<=Q; part of my process. I will try the code you gave me and compare it to what I have and see how I can fix mine. Thanks for your help.