D Flip Flop

There could be a great many things wrong with it ... but you haven't posted a sufficient amount of code.

For example the statement Q <= 0 is not valid for std_logic, it should be Q <= '0', but then again, perhaps you have included a conversion library ...

Post a complete example, rather than a code snippet.

Here's how I would normally write this piece of code;

-- Start with only this library (you can get fancy later)
library ieee;
use ieee.std_logic_1164.all;
....
process(clk, reset)
begin
  if (reset = '1') then
    q <= '0';
  elsif rising_edge(clk) then
     if ((a = '1') and (b = '1')) then
        q <= d;
     end if; 
  end if;
end process;

Note the use of elsif, and also note that I've assumed a and b are std_logic, so to turn them into boolean I've compared them with a std_logic '1'. I do this out of habit, the syntax you have used might be allowed with VHDL-2008. Play with this example and see what you are allowed to do and what you cannot.

Cheers,

Dave