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Altera_Forum
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10 years ago

CycloneV ALTLVDS_TX Channels Fitter Error 175020

Hi! I am using CycloneV SEBA4 device and implementing a design with ALTLVDS_TX and RX IPs with 5 channels. I am using IOBanks 4A,3B and 5A with PLL of bank 4A with IP internal PLL settings. All...
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Altera_Forum
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9 years ago

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Did you assign PIN_AE7 to lvds_tx_master_0_lvds_out_lvds_tx[3] and it is the negative differential signal of the LVDS pair?

If the answer is yes, just remove lvds_tx_master_0_lvds_out_lvds_tx[3] from your Verilog (VHDL) as output port.