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Honored Contributor
Honored ContributorCycloneV ALTLVDS_TX Channels Fitter Error 175020
Hi! I am using CycloneV SEBA4 device and implementing a design with ALTLVDS_TX and RX IPs with 5 channels. I am using IOBanks 4A,3B and 5A with PLL of bank 4A with IP internal PLL settings. All...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Did you assign PIN_AE7 to lvds_tx_master_0_lvds_out_lvds_tx[3] and it is the negative differential signal of the LVDS pair? If the answer is yes, just remove lvds_tx_master_0_lvds_out_lvds_tx[3] from your Verilog (VHDL) as output port.
