Honored Contributor
Honored ContributorHi Joel,
--- Quote Start --- in the meantime I was analyzing the possibilities regarding another ADCs. There is however one thing that I need to clear first. Could I implement 3.125 Gbps transceivers (Cyclone V GX) as a SerDes interface for the HMCAD 1511 ADC ? I don't have any experiences implementing transceivers but it looks promising. What do you think ? --- Quote End --- Don't bother trying to interface using the transceivers. High-speed transceivers are not just "faster" LVDS channels. FPGA LVDS channels can be used to interface to an ADC like this Hittite part because a group of LVDS receivers can be used synchronously per the document I referred you to above. FPGA SerDes receivers are essentially independent entities. They like to be operated in lock-to-data mode, where the clock is recovered from the data. This means that the data has to be modulated such that it has enough transitions that the clock can be recovered and the receiver PLL can remain locked. I'm currently developing an interface to the Hittite 20GHz ADC http://www.hittite.com/products/view.html/view/hmcad5831lp9be using 10Gbps Stratix IV GT transceivers ... and its not a "simple" problem :) Cheers, Dave
