Cyclone V readout of 300MHz DDR interface not meeting timing

Yeah, that's the problem. To get the high-speeds, a low-skew dedicated clock goes from the PLL to the I/O. It doesn't drive all I/O(but there are multiple PLLs that can do this, so as long as they're close to the I/O it should work).

I was thinking of trying to cascade the PLLs or something like that, but to be honest, if this is just a test environment, going back to DDR and a design that fails timing(and probably pretty badly) will still probably work in hardware. Since the board's laid out, that's what I would try first.