Honored Contributor
Honored ContributorGreat help, as always, Rysc. Thanks!
--- Quote Start --- 1) SERDES of 2 results in a DDIO implementation, so that won't work. You need to go with a SERDES of 4 or higher and you'll get the dedicated logic. (Are you running your Cyclone V core at 300MHz? Do-able, but not easy.) The SERDES of /2 limitation didn't used to be a limitation because the rates you need the real SERDES logic for were so high you would need to do a higher deserialization rate anyway. There's kind of a donut hole now where in theory you could be required to use SERDES, yet your fabric is fast enough it could handle /2 internally. It doesn't happen often, but I recommend just going down to /4 and immediately muxing it back up to /2 data rate. --- Quote End --- I'm actually already splitting my datastream by 4x a little further down the line, because I discovered early in the design process that only the simplest of logic designs could meet timing at 300MHz. I guess I'll just move that split right up to the output of the SERDES. --- Quote Start --- 2) Yes, but I believe they're available on all dedicated LVDS receivers, so if your board is using the LVDS receivers, the SERDES logic should be there. (It can be a little more complicated than that, i.e. the SERDES clock can't drive LVDS receivers on opposite sides of the die, but your board probably isn't laid out like that anyway). Throw it down in your design, put a deserialization of /4(you don't even have to hook up the extra 2 bits for now) and see if it fits. --- Quote End --- Unfortunately, quartus II gives me the following error with the SERDES for the current pin assignment: Error (175001): Could not place PLL LVDS output Info (175028): The PLL LVDS output name: DDR_PLL2:DDR_PLL2_0|DDR_PLL2_0002:ddr_pll2_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_LVDS_OUTPUT Error (175006): Could not find path between the PLL LVDS output and destination pin Info (175027): Destination: pin ADC_D[1] Info (175015): The I/O pad is constrained to the location PIN_K12 due to: User Location Constraints (PIN_K12) I've attached a screenshot from the pin planner, where I've highlighted the pins used in the source synchronous interface. The ADC DDR inputs to the FPGA are the ones closer to the upper left corner (use DIFFIO_RX_*_p and n), and the ssync clock is the differential pair closer to the bottom right (uses CLK5p and n) . I'm guessing the problem is that these are so far apart. For the current board revision, is there a way to get the clock up to the SERDES blocks for the data bus? The desire here is to debug the rest of the board/firmware as much as possible before the next board revision. For the next board revision, I'll still need the ssync clock to end up on one of the pins mapped to the HSMC port of the Terasic SoCKit I'm using. Would the best strategy be to try compiling with a few different pin locations for the ssync clock signal, and just see if quartus can fit it? Maybe there's a better/faster/more sophisticated strategy that can be recommended. Thanks!
