Cyclone V readout of 300MHz DDR interface not meeting timing

1) SERDES of 2 results in a DDIO implementation, so that won't work. You need to go with a SERDES of 4 or higher and you'll get the dedicated logic. (Are you running your Cyclone V core at 300MHz? Do-able, but not easy.) The SERDES of /2 limitation didn't used to be a limitation because the rates you need the real SERDES logic for were so high you would need to do a higher deserialization rate anyway. There's kind of a donut hole now where in theory you could be required to use SERDES, yet your fabric is fast enough it could handle /2 internally. It doesn't happen often, but I recommend just going down to /4 and immediately muxing it back up to /2 data rate.

2) Yes, but I believe they're available on all dedicated LVDS receivers, so if your board is using the LVDS receivers, the SERDES logic should be there. (It can be a little more complicated than that, i.e. the SERDES clock can't drive LVDS receivers on opposite sides of the die, but your board probably isn't laid out like that anyway). Throw it down in your design, put a deserialization of /4(you don't even have to hook up the extra 2 bits for now) and see if it fits.