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I need to update that document. The DDIO are not getting faster in newer generations, and are actually probably slower. (The problem is that performance is not dictated by raw speed, but how much variation there is in paths, which the smaller geometries seem to have more of). That being said, all 28nm families have dedicated altlvds hardware to help overcome this. These should run much faster. Cyclone V devices are spec'd in the Data Sheet at 875, 840 and 640 Mbps depending on speed grade. So instantiate the altlvds block.
Also note that the timing is completely different with this hardware. I think the ssync user guide talks about this. It should be much easier, as most of the time people don't apply any constraints and just look at the Report RSKM(also explained in the Cyclone V Data Sheet)
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Thanks! I'm starting to looking into the altlvds block now.
Two questions:
1.) How does the SERDES factor used with altlvds change the timing margin of the interface? My application on the Cyclone V SX only really needs a SERDES factor of 2, but I could split the datastream with a larger SERDES factor of, say 4, or 8, if there is a timing advantage to larger SERDES factors.
2.) Are the allowable physical pin locations for the altlvds interface more restrictive for the dedicated LVDS hardware than for the DDR hardware in the IOEs? I already have a daugther card with traces corresponding to pin locations I've chosen for this project, and would like to try to get this particular board to meet timing, if possibile...
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