Cyclone V readout of 300MHz DDR interface not meeting timing

I need to update that document. The DDIO are not getting faster in newer generations, and are actually probably slower. (The problem is that performance is not dictated by raw speed, but how much variation there is in paths, which the smaller geometries seem to have more of). That being said, all 28nm families have dedicated altlvds hardware to help overcome this. These should run much faster. Cyclone V devices are spec'd in the Data Sheet at 875, 840 and 640 Mbps depending on speed grade. So instantiate the altlvds block.

Also note that the timing is completely different with this hardware. I think the ssync user guide talks about this. It should be much easier, as most of the time people don't apply any constraints and just look at the Report RSKM(also explained in the Cyclone V Data Sheet)