Forum Discussion
Altera_Forum
Honored Contributor
10 years agoAn update ... Altera support said, "we ran the script and it was fine ... " and it turns out that that is a true statement. The msim_setup.tcl script adds a "com" command to ModelSim, which compiles the model, and an "elab" command, which elaborates the design (runs the vsim command). And then you can run the simulation. But this is pointless because it doesn't run a test bench.
But I have worked out a solution. I started with the list of files in plain_files.txt. Rather than try to compile them all into some other library, I just added them all to a ModelSim project, in the order of compilation, and they get analyzed into the work library. Then I added the source that instantiates the core, and finally the test bench source. All of it compiled fine. Running vsim by itself isn't sufficient; while a lot of libraries are shown in the library page, they're invisible to the design unless you explicitly call them out on the vsim command line. Conveniently, though, you can copy that command line from msim_setup.tcl at the elab command. I created a ModelSim simulation configuration which calls out all of those libraries. And that all works. I suppose it's because it's all SystemVerilog, which doesn't have VHDL's libraries concept. If it was all VHDL, all of the models for the transceiver could be analyzed into a library called xcvr, and maybe create a package with the component declarations for them all (and analyze that package source into the library), and in your test bench, you use the library and package in the usual way and instantiate the components in the package in the usual way. anyways, what a pain.