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BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V: FPGA to SDRAM interface not working

Hello. Part: Cyclone V 5CSXFC5D6F31C7, about 85% utilized. I've written RTL in verilog for a simple MM interface from the FPGA to SDRAM 1 HPS interface. I created a test bench utilizing an MM DRA...
BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi Anil,

Instead of using the HPS simulation model, I used the intel Avalon Slave BFM simulation model in my simple test bench. It took a while to get it to do what I want but I was finally able to understand what my Avalon Master interface was lacking. I changed the interface to burst 16 and fill little SRAM Cache's spread throughout the design.

Simulation showed that it worked and after finding a connection error at the top level of the part, I was able to get the DRAM interface working.

I have not tested this patch, but when I get the opportunity, I'd like to test with it to determine exactly how much overhead the FPGA to DRAM interface has to make sure my burst logic is efficient enough in all the corner cases.

When I get a chance to try this, I'll post an update.

Thanks much.