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BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone V: FPGA to SDRAM interface not working

Hello. Part: Cyclone V 5CSXFC5D6F31C7, about 85% utilized. I've written RTL in verilog for a simple MM interface from the FPGA to SDRAM 1 HPS interface. I created a test bench utilizing an MM DRA...
BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Quick update: I removed the PCIe stuff from the Platform Designer file and attempted to generate a test bench for just the HPS and my FPGA implementation.

Now I get this error:

Error: fpga_interfaces: add_fileset_file: No such file /opt/intelFPGA/20.1/ip/altera/mentor_vip_ae/axi3/bfm/mgc_common_axi.sv
    while executing
"add_fileset_file mgc_common_axi.sv SYSTEM_VERILOG PATH $MENTOR_VIP_DIR/axi3/bfm/mgc_common_axi.sv"
    ("if" then script line 3)
    invoked from within
"if {$include_axi_bfm} {
      add_fileset_file questa_mvc_svapi.svh SYSTEM_VERILOG PATH $MENTOR_VIP_DIR/common/questa_mvc_svapi.svh
      add_fileset_..."
    (procedure "add_files_to_simulation_fileset" line 33)
    invoked from within
"add_files_to_simulation_fileset $data(interfaces)"
    (procedure "sim" line 41)
    invoked from within
"sim CPU_Subsys3_sim_hps_0_fpga_interfaces"