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Altera_Forum
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15 years ago

cyclone III slow memory

I created a simple project with only a m9k memory block to help trouble shoot my larger project. The memory block is set up so that read and write clocks are seperate. All inputs are registered but...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I found that I had changed the clock frequency in the test bench but not in the ALTPLL. So you were right there was some conflict in the simulation. I was able to get it operate at 274Mhz in simulation internally, but there was a delay in addressing to output of 9.7 ns and the output at the pins could not operate that fast.