Cyclone III asynchronous input signal synchroinization problem.

Thank's for the term difference explanation. I make the next version of some IIC blocks that is fully synchronized. The clock source is PLL (10MHz). I am afraid to use any other sources (combinational logic or triggers) to make clock now.

The IIC signals are synchronized by two triggers per signal in IIC_Parser module. Then they are parsed by edges on negedge CClk signal (edge detectors in IIC_Parser module). After that the negedge IIC_Clock signals are used to make counting. The counting process flows by posedge CClk. I hope it is possible to secure the Tsu and Th condition by using the different CClk edges in synchronizer and counter. And the synchronization IIC signals on CClk have to prevent the slow edge with superimposed noise false counting. No more errors on the oscillogram is observed.

The other signals of the parser module will be used later. I will read any hints or comments about my design with pleasure if any. The start topic problem is solved.