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First of all why I think I saw metastability. I connect to IIC clock line the 0.01uf capacitor and receive this oscillogram. It is clearaly seen (on the pic 1), that when the voltage reach the Vcritical value (1.275V) a number of false clock edges occur. It looks like the input trigger have no “band gap“ between logic 0 and logic 1 voltages. I think that without this capacitor the same processes occurs. But the quantity of “false edges” strongly decreases especially with decreasing the pull-up resistors value.
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Now the effect can be clearly seen. It has nothing to do with metastability, just a slow edge with superimposed noise. Most logic families have a minimal slew rate for input signals to be detected as clean edge, the number is in a 0.1 V/ns range for fast logic, e.g. FPGAs. It's true that ST inputs can be used to process signals with slow risetime, but they are analog blocks which would cause additional unwanted delay. In some cases enabling the bus hold feature can work as a poor man's schmitt trigger. The I2C pull-up resistors must be strong enough to source the bus hold overdrive current.
But much more effectively, you can debounce the noisy bus lines in digital logic. Usually it's sufficient to sample the bus lines with a moderate clock speed of a few MHz and detect changes in a state machine. So it's guaranteed that each input edge is detected once and only once.
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What about the second register in synchronizer? I can’t understand it’s function in the scheme. Nothing changes except increased delay time between input clock edge and synchronized signal edge when I add it in design. (pic 2)
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The concept of synchronizer chains is e.g. discussed in the Quartus Software Handbook in chapter
managing metastability with the quartus ii software. Generally, two is the minimal amount of registers considered safe.
Regarding "using data as clock", there are basically two issues:
- Timing. Usually data inputs of registers are driven by other registers, directly or through combinational logic. When also the clock input is driven from register outputs, you have difficulties to keep setup- and hold-time requirements. Becomes worse due to arbitrary logic and routing delays.
- Glitches. FPGA logic elements are programmable look-up tables. They are not guaranteed to have a glitch-free output if more than one input signal to a LE changes.
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