Cyclone III asynchronous input signal synchroinization problem.

The waveforms are hard to read with the analog traces overlaying the digital. I would really prefer separated traces.

I presume you don't see actually metastability in the non-synced case rather than failing edge detection. Although metastability exists, you'd have to struggle hard to catch it on the oscilloscope screen because the probability is very small. Nevertheless you have a synchronization problem.

The design has basically the right topology in terms of signal synchronization, except for the point that a standard synchronizer uses double instead of single registering. The difference matters for metastable events which may happen with a likelihood 1:10^6 or 1:10^9.

So why does it fail? I'm willing to look at better readable and annotated waveforms, trying to understand what exactly happens.

I see however a general problem of your design. I fear it doesn't have any debouncing logic for the I2C lines, which is absolutely necessary regarding the slow edges, and at least implicitely required by the timing specification of the I2C standard.

P.S.: I completely agree with chris72 that clocking of the bit counter with a non-clock is most likely causing the observed problem. You should replace it with a fully synchronous construct where all register clock inputs are only feeded by cclk, as said.

The design looks like copied from an discrete logic IC wire entanglement. In this technolgy, you could place a small capacitors to filter unwanted glitches in a data signal used as clock. Unfortunately that's not possible in a FPGA design.