Cyclone II embedded RAM synthesize away

It's not really clear, what you try to achieve, thus my answer may partly miss your problem.

Generally, if the output of your RAM isn't connected to the outer world, it will be synthesized away. That shouldn't have any consequences for the design's behaviour, except in simulation of internal nodes. If you want to know the resource requirements of your module, you must connect it up to the top and have any output pins depending on it.

I also don't know, what you're intending with internal threestate drivers. Phsyically, no FPGA of any vendor has internal busses. But you may use them in the RTL and they are translated to multiplexers and point-to-point connections by the HDL compiler, if you find these construct useful to describe your logic. Of course, unequivocal enable conditions for the internal threestate drivers respectively inferred multiplexers must exist.