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Jeff9's avatar
Jeff9
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3 years ago
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Cyclone 10 GX EMIF Design Example: I/O assignment errors

Hello, I'm following the Cyclone 10 GX EMIF IP Design Example User Guide in the below web page. 1. Design Example Quick Start Guide for External Memory Interfaces... (intel.com) The EMIF projec...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Jeff,


    No, you should not choose "Project Template".


    I am thinking that you are not opened the generated example design.

    If you are referring to Figure 3 in Section 1.3, there is a path to where the generated example design is created.

    Usually, the project design is located in emif_0_example_design/qii/ed_synth.qpf


    Can you check the design in this path?


    Regards,

    Adzim


  • Jeff9's avatar
    Jeff9
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Adzim,

    Thank you for the answer. When I create the project, the type was empty project as the user guide. Do you mean I had to choose "Project template" instead of "Empty project"?

    I applied a DDR3 preset (DDR3-1600K CL11 Component 1CS 4Gb (256Mb x16)) with the platform designer as you suggested. My board has two 256Mb x16 DDR3 ICs. So, the DQ width was changed from 16 to 32 at the "Memory" tab in EMIF FPGA IP.

    "Generate Example Design" and "Generate HDL" were done again with the updated IP. However, I still see the similar compilation errors. Do you have some other suggestions for this?

    Regards,

    Jeff